1. Field of the Invention
The present invention generally relates to an overlay measuring mark and its method. Specially, it relates to an overlay measuring mark and a method of measuring an overlay error between multi patterns in a semiconductor device using the overlay measuring mark.
2. Description of Related Art
As integrated circuit processing becomes more and more precise and the dimension of the various circuit alignment of each process layer to preceding process layers becomes greater. In order to facilitate alignment of the various process layers, small alignment images are typically included in the photomasks used to photolithigraphically produce each layer, with each such image being intended to produce on the wafer substrate an alignment attribute which a corresponding attribute of a subsequent layer can be aligned.
Generally, a semiconductor device is fabricated by complicated process wherein a plurality of light-exposure masks are repeatedly aligned by a stepper. The stepper, which is limited light-exposing apparatus operable in a step-and-repeat manner repeatedly moves a stage in a x-y direction so as to align the masks prior to exposure to light. By means of the stepper, a wafer is aligned in a manual or automatic manner on the basis of an alignment mark or called overlay measuring mark. At the moment, an error may be generated by mechanical motion of the stage during alignment. If this alignment error exceeds an allowable limit, a defect may be generated in the semiconductor device.
Usually, an overlay measuring mark, involving an upper mark which is overlapped with a lower mark, measures alignment error. The control range of overlay accuracy for misalignment acts on the design rule of the semiconductor device and is typically in a range of 20 to 30%. The measurement of misalignment using alignment marks is carried out in accordance with either a visual checking method using vernier alignment marks or an automatic checking method using box-in-box or box-in-bar alignment marks. The misalignment is compensated based on the result of the measurement.
FIG. 1 and FIG. 2 show an inner and an outer masks combined to form an overlap measuring masks by light exposure masks in the prior art. FIG. 3 shows the overlap measuring masks implemented on the wafer to measure alignment error.
In FIG. 1, a light exposure mask 1 comprises a transparent part 2 and an obscure part 3 used to generate the outer mask. And in FIG. 2, a light exposure mask 11 comprises a transparent part 12 and an obscure part 13 used to generate the inner mask.
In FIG. 3, an etch layer with on a wafer substrate 21 is provided. The light exposure mask 1 is first used as a pattern to etch the etch layer, thereby an outer mark 22 in FIG. 3 is formed. By the same method, the light exposure mask 11 is next used as a pattern to etch the rest etch layer, thereby an inner mark 23 in FIG. 3 is formed.
At this moment, reference points on the inner and outer mark 23 and 22 on the substrate 21 can measure alignment error. In general, overlay measurement is applied in wafer fabricating processes to estimate alignment error between two or more patterns on different layers. FIG. 4 and FIG. 5 illustrate a prior art method of measuring an overlay error of multi patterns.
An overlay measurement mark is formed on a scribe line of a wafer using a plurality of masks, with the masks identical to the one used in the formation of patterns on a product die of the wafer. As shown in FIG. 5 to form overlay measuring marks according to the lay-out of FIG. 4, an outer measuring mark 51 corresponding to the conductive region H of FIG. 4 is formed on a scribe line (not shown) using a pattern mask. And after that, an inner overlay measuring mark 52 corresponding to contact regions F and G of FIG. 4 is formed on the scribe line using a contact mark, with the inner mark 52 forming from the inside the outer mark 1. The outer mark 1 is formed with conductive material while the inner mark 52 is formed with photoresist.
In the overlay measurement method, distance A and A' between the two marks 51 and 52 are measured as a degree of overlay in the x-axis, and the difference A-A' between the two distance is taken as an overlay error in the x-axis. Similarly, distance B and B' between the two marks 51 and 52 are measured as a degree of overlay in the y-axis, and the difference B-B' between the two distances is taken as an overlay error in the y-axis.
However, the overlay error created by the conventional overlay measuring marks can not be available with more precision in semiconductor fabrication at these times. Since the size of the overlay measuring marks is larger than ten times of the size of the elements on fabricated wafer, the overlay error measured from the conventional overlay measuring marks can not show real and slight overlay error between different layers. For example based on the outer mark 22 in FIG. 3, the edge of the outer mark 22 is 30 um.times.30 um and in general such outer mark is used in 0.3 um semiconductor fabrication. If the desired size of elements on wafers is reduced, i.e. smaller than 0.3 um, the slight overlay error can not be measured since the resolution of optical devices or the recognition ability of human eyes is limited to tell such slight overlay error. Namely, the conventional outer mark 22 and inner mark 23 in FIG. 3 will not be suit for smaller than 0.3 um semiconductor fabrication.